View ADL5202XCPZ-R7_6983887.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

31.5 db range, 0.5 db step size programmable vga preliminary technical data adl5202 rev. pre information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features dual independent digitally controlled vgas ?11.5 to 20 db gain range 0.5 db step size 0.1 db 150 differential input and output 6 db noise figure @ maximum gain oip3 of 50 dbm at 200 mhz ?3 db bandwidth of 700 mhz multiple control interface options parallel 6-bit control interface serial peripheral interface gain step up/down interface wide input dynamic range high performance power mode power-down control single 5 v supply operation 40-lead lfcsp 6 x 6 mm package applications differential adc drivers high if sampling receivers high output power if amplification instrumentation functional block diagram pw p a r a llel, serial, +20 db adl5202 up/down interface vcc gnd vina+ vina? upa vouta+ vouta? vouta+ vouta? 0->31.5db serial/parallel/up-down interface & decode +20 db 0->31.5db serial/parallel/up-down interface & decode parallel, serial, up/down interface pwu pwupa pb voutb+ voutb+ voutb? voutb ? vinb+ vinb? figure 1. general description the adl5202 is a digitally controlled, variable gain wide bandwidth amplifier that provides precise gain control, high ip3 and low noise figure. the excellent distortion performance and high signal bandwidth makes the adl5202 an excellent gain control device for a variety of receiver applications. for wide input dynamic range applications, the adl5202 pro- vides a broad 31.5 db gain range with 0.5 db resolution. the gain is adjustable through multiple gain control interface options: parallel, serial peripheral interface, or gain step up/down. using a high speed sige process and incorporating proprietary distortion cancellation techniques, the adl5202 achieves better than 50 dbm output ip3 at frequencies approaching 200 mhz for all gain settings. the adl5202 is powered on by applying the appropriate logic level to the pwup pin. the quiescent current of the adl5202 is typically 160 ma. it may be configured for higher quiescent current of 220 ma, in high performance power mode, for more demanding applications. when powered down, the adl5202 consumes less than 18 ma and offers excellent input to output isolation. the gain setting is preserved when powered down. fabricated on an adis high speed sige process, the adl5202 provides precise gain adjustment capabilities with good distortion performance. the adl5202 amplifier comes in a compact, thermally enhanced 6 x 6mm 40-lead lfcsp package and operates over the temperature range of ?40c to +85 c
adl5202 preliminary technical data rev. pre | page 2 of 13 table of contents functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 6 ? thermal resistance ...................................................................... 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? digital interface overview ...............................................................9 ? typical performance characteristics ........................................... 10 ? evaluation board ............................................................................ 11 ? evaluation board control software ......................................... 11 ? schematics and artwork ........................................................... 11 ? outline dimensions ....................................................................... 13 ? ordering guide ............................................................................... 13 ?
preliminary technical data adl5202 rev. pre | page 3 of 13 specifications v s = 5 v, t = 25c, z s = z l = 150 at 100mhz, pm = 0 v, 2 v p-p differential output unless otherwise noted. table 1. parameter conditions min typ max unit dynamic performance ?3 db bandwidth v out < 2 v p-p (5.2dbm) 700 mhz slew rate tbd v/nsec input stage pins vin+ and vin- maximum input swing gain code = 111111 8 v p-p differential input resistance differential 150 common-mode input voltage 1.5 v cmrr gain code = 000000 tbd db gain maximum voltage gain gain code = 000000 20 db minimum voltage gain gain code = 111111 ?11.5 db gain step size 0.5 db gain flatness 30 mhz < f c < 200mhz tbd db gain temperature sensitivity gain code = 000000 tbd mdb/ c gain step response for v in = 0.2v, gain code 111111to 000000 15 ns gain conformance error normalized to 10db gain step 0.03 db phase conformance error normalized to 10db gain step 1.0 deg output stage pins out+ and out- output voltage swing at p1db, gain code = 000000 10 v p-p differential output resistance differential 150 noise/harmonic performance 46 mhz [high performance power mode] gain code = 000000, lp = low noise figure 6 db second harmonic v out = 2 v p-p ?90 dbc third harmonic v out = 2 v p-p ?100 dbc output ip3 tbd dbm output 1 db compression point 18.6 dbm 46 mhz [nominal power mode] gain code = 000000, pm = high noise figure tbd db second harmonic v out = 2 v p-p -90 dbc third harmonic v out = 2 v p-p -100 dbc output ip3 tbd dbm output 1 db compression point tbd dbm noise/harmonic performance 70 mhz [high performance power mode] gain code = 000000, lp = low noise figure 6 db second harmonic v out = 2 v p-p ?88 dbc third harmonic v out = 2 v p-p ?100 dbc output ip3 46.4 dbm output 1 db compression point 19.7 dbm
adl5202 preliminary technical data rev. pre | page 4 of 13 parameter conditions min typ max unit 70 mhz [nominal power mode] gain code = 000000, pm = high noise figure tbd db second harmonic v out = 2 v p-p -88 dbc third harmonic v out = 2 v p-p -100 dbc output ip3 40 dbm output 1 db compression point tbd dbm noise/harmonic performance 140 mhz [high performance power mode] gain code = 000000, lp = low noise figure 6.4 db second harmonic v out = 2 v p-p ?88 dbc third harmonic v out = 2 v p-p ?97 dbc output ip3 tbd dbm output 1 db compression point 19.7 dbm 140 mhz [nominal power mode] gain code = 000000, pm = high noise figure tbd db second harmonic v out = 2 v p-p -88 dbc third harmonic v out = 2 v p-p -97 dbc output ip3 tbd dbm output 1 db compression point tbd dbm noise/harmonic performance 170 mhz [high performance power mode] gain code = 000000, lp = low noise figure 6.5 db second harmonic v out = 2 v p-p ?82 dbc third harmonic v out = 2 v p-p ?97 dbc output ip3 46.7 dbm output 1 db compression point 19.7 dbm 170 mhz [nominal power mode] gain code = 000000, pm = high noise figure tbd db second harmonic v out = 2 v p-p -77 dbc third harmonic v out = 2 v p-p -95 dbc output ip3 39.7 dbm output 1 db compression point tbd dbm noise/harmonic performance 240 mhz [high performance power mode] gain code = 000000, lp = low noise figure 6.9 db second harmonic v out = 2 v p-p ?78 dbc third harmonic v out = 2 v p-p ?93 dbc output ip3 tbd dbm output 1 db compression point 19.7 dbm 240 mhz [nominal power mode] gain code = 000000, pm = high noise figure tbd db second harmonic v out = 2 v p-p -73 dbc third harmonic v out = 2 v p-p -93 dbc output ip3 tbd dbm output 1 db compression point tbd dbm
preliminary technical data adl5202 rev. pre | page 5 of 13 parameter conditions min typ max unit noise/harmonic performance 300 mhz [high performance power mode] gain code = 000000, lp = low noise figure 7.3 db second harmonic v out = 2 v p-p ?70 dbc third harmonic v out = 2 v p-p ?88 dbc output ip3 tbd dbm output 1 db compression point 19.5 dbm 300 mhz [nominal power mode] gain code = 000000, pm = high noise figure tbd db second harmonic v out = 2 v p-p -68 dbc third harmonic v out = 2 v p-p -88 dbc output ip3 tbd dbm output 1 db compression point tbd dbm noise/harmonic performance 380 mhz [high performance power mode] gain code = 000000, lp = low noise figure 7.8 db second harmonic v out = 2 v p-p ?67 dbc third harmonic v out = 2 v p-p ?80 dbc output ip3 tbd dbm output 1 db compression point 18.4 dbm 380 mhz [nominal power mode] gain code = 000000, pm = high noise figure tbd db second harmonic v out = 2 v p-p -65 dbc third harmonic v out = 2 v p-p -80 dbc output ip3 tbd dbm output 1 db compression point tbd dbm enable interface pin pwup enable threshold minimum voltage to enable the device 1.4 v pwup input bias current tbd na gain control interface digital pins v ih minimum voltage for a logic high 1.4 v v il maximum voltage for a logic low 0.8 maximum input bias current tbd na power-interface supply voltage 4.5 5.5 v quiescent current pm = low (high performance power mode) 220 ma pm = high (nominal power mode) 160 ma power down current pwup low 18 ma
adl5202 preliminary technical data rev. pre | page 6 of 13 absolute maximum ratings thermal resistance table summary table 2. parameter rating supply voltage, v pos 5.5 v pwup, digital pins -0.6 to (v pos + 0.6v) input voltage, v in+ ,v in- -0.6 to +3.1v internal power dissipation tbd mw ja (exposed paddle soldered down) tbdc/w ja (exposed paddle not soldered down) tbdc/w jc (at exposed paddle soldered down) tbdc/w maximum junction temperature tbdc operating temperature range C40c to +85c storage temperature range C65c to +150c ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja jc unit esd caution stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
preliminary technical data adl5202 rev. pre | page 7 of 13 pin configuration and fu nction descriptions ? exposed p addle nc = no connect 1 2 a4 3 a5 4 mode1 5 mode0 6 pm 7 gnd 8 sido/b5 9 sclk/b4 10 23 vpos 24 vpos 25 vpos 26 vpos 27 vpos 28 vpos 29 30 22 21 11 a_b/b2 12 _b/b1 13 t_b/b0 15 17 w upb 16 18 gnd 19 20 14 atchb 33 pw upa 3 4 gnd 35 36 37 latcha 38 updn _dat_a/a0 39 updn_clk_ a/a1 40 fa_a/a2 32 31 gs0/f updn_clk updn_da p l pin 1 indicator csa/a3 gs1/csb/b3 vinb? vinb+ adl5202 v outb? v outb+ vouta+ vouta? vina+ vina? top view (not to scale) utb+ utb? v o u t a + vouta? vo vo figure 2. 40 lead lfcsp table 4. pin function descriptions pin o. nemonic description 1 csa /a3 multi function pin: when serial mode is enabled, a logic low on this pin selects channel a. in parallel mode, this bit 3 for the gain control interface. 2 a4 bit 4 for channel a parallel gain control interface. 3 a5 bit 5, (msb) for channel a parallel gain control interface. 4 mode1 msb for the mode control parallel, spi, up/down interface. 5 mode0 lsb for the mode control parallel, spi, up/down interface. 6 pm a logic low on this pin enables high performance mode. a logic high enables nominal performance mode. 7, 18, 33, ep 1 gnd ground 8 sdio/b5 multi function pin: when csa or csb is pulled low, sdio is used for reading and writing to the spi port. in parallel mode, this bit is 5 (msb) for the channel b parallel gain control interface. 9 sclk/b4 multi function pin: when spi mode is selected this pin is the serial clock input. in parallel mode this pin is bit 4 for channel b gain interface. 10 gs1/ csb /b3 multi function pin: when the up/down mode is enabled, this pin is the msb for the gain step size control. when serial mode is enabled, a logic low on this pin selects channel b. in parallel mode, this is bit 3 of the gain control interface. 11 gs0 fa_b/b2 multi function pin: when the up/down mode is enabled, this pin is the lsb for the gain step size control. a logic high enables the channel b spi port fast attack mode. in parallel mode this pin is bit 2 for channel b gain interface. 12 updn_clk_b/b1 multi function pin: this pin is the clock interface for channel b updn function. in parallel mode this pin is bit1 for channel b gain interface. 13 updn_dat_b/b0 multi function pin: this pin is the data pin for channe l b updn function. in parallel mode this is bit 0 for channel b gain interface. 14 latchb latch, a low input results in gain ch ange. a high input results in no gain change. 15 vinb? channel b negative input. 16 vinb+ channel b positive input.
adl5202 preliminary technical data rev. pre | page 8 of 13 pin no. mnemonic description 17 pwupb channel b power up. a logic high on this pin enables the part. 19, 21 voutb+ channel b positive output. 20, 22 voutb? channel b negative output. 23, 24, 25, 26, 27, 28, vpos positive power supply. 29, 31 vouta+ channel a positive output 30, 32 vouta? channel a negative output 34 pwupa channel a power up. a logic high on this pin enables the part. 35 vina+ channel a positive input. 36 vina? channel a negative input. 37 latcha latch, a low input results in gain ch ange. a high input results in no gain change. 38 updn_dat_a/a0 multi function pin: this pin is the data pin for channe l a updn function. in parallel mode this is bit 0 for channel a gain interface. 39 updn_clk_a/a1 multi function pin: this pin is the clock interface for channel a updn function. in parallel mode this pin is bit1 for channel a gain interface. 40 gs0 fa_b/b2 multi function pin: when the up/down mode is enabled, this pin is the lsb for the gain step size control. a logic high enables the channel a spi port fast attack mode. in parallel mode this pin is bit 2 for channel a gain interface. 1 exposed paddle
preliminary technical data adl5202 rev. pre | page 9 of 13 digital interface overview the adl5202 dvga has three digital control interface options: ? parallel control interface ? serial peripheral interface ? gain step up/down interface the digital control interface selection is made via 2 digital pins, mode1 and mode0, as shown in table 5 . there are two common digital control pins, pm and pwup. pm selects between two power modes. pwup is a power up pin. the gain code used is 6 bit binary. physical pins are shared between 3 interfaces resulting in as many as 3 different functions per digital pin (see table 4 ) table 5. digital control interface selection truth table mode1 mode0 interface 0 0 parallel 0 1 serial (spi) 1 0 up/down 1 1 up/down parallel digital interface the parallel digital interface uses 6 gain control bits and a latch pin per amplifier. the latch pin controls whether the input data latch is transparent or latched. in transparent mode, gain changes as input gain control bits change. in latched mode, gain is determined by the latched gain setting and does not change with changing input gain control bits. serial peripheral interface (spi) the spi uses 3 pins (sdio, sclk, and /csa or /csb). the spi data register consists of 2 bytes: 6 gain control bits, 2 attenuation step size address bits, 1 read/write bit, and 7 do not care bits. the spi uses a bidirectional pin, sdio, for writing to the spi register and for reading from the spi register. in order to write to the spi register, csa or csb needs to be pulled low and 16 clock pulses must be applied. individu al channel spi registers can be selected by pulling low csa or csb . by simultaneously pulling low the csa and csb pins, the same data can be written to both spi registers. in order to read the spi register value, the r/w bit needs to be set high, csa or csb needs to be pulled low, and the part clocked. once the register has been read out the r/w bit needs to be set low and spi put in write mode. note that there is only one sdio pin. read back from the registers should be done individually. spi fast attack mode is controlled by fa_a or fa_b. a logic high on the fa pin results in an attenuation selected by fa1 and fa0 bits in the spi register. table 6. spi 2-bit attenuation step size truth table fa1 fa0 step size (db) 0 0 2 0 1 4 1 0 8 1 1 16 up/down interface the up/down interface uses two digital pins to control the gain. gain is increased by a clock pulse on updn_clk (rising and falling edges) when updn_dat is high. gain is decreased by a clock pulse on updn_clk when updn_dat is low. reset is detected by a rising edge latching data having one polarity with the falling edge latching the opposite polarity. reset results in minimum gain code 111111 bin . updn_dat updn_clk up dn reset figure 3. up/down timing the step size is selectable by pins gs1 and gs0. the default step size is 0.5db. the gain code count will rail at the top and bottom of the control range. table 7. step size control truth table gs1 gs0 step size (db) 0 0 0.5 0 1 1 1 0 2 1 1 4 figure 4. 16- bit spi register
adl5202 preliminary technical data rev. pre | page 10 of 13 typical performance characteristics 20 25 30 35 40 45 50 55 42024 oip3 (dbm) p out per tone (dbm) 6 av = +4.5db av = +20db av = 0db av = 3.5db av = 11.5db ? ? figure 5. oip3 vs. power @ 5 gains 0 5 10 15 20 25 0 50 100 150 200 250 300 350 400 450 500 op1db (dbm) frequency (mhz) figure 6. p1db vs. frequency at max gain 30 32 34 36 38 40 42 44 46 48 50 0 5 10 15 20 oip3 (dbm) gain (db) 100 mhz performance mode 200 mhz performance mode 100 mhz nominal mode 200 mhz nominal mode 10 ? 5 ? figure 7. oip3 vs. gain 4 5 6 7 8 9 10 0 50 100 150 200 250 300 350 400 450 500 noise figure (db) frequency (mhz) figure 8. noise figure vs. frequency at max gain 45 40 35 30 25 20 15 10 5 0 0 100 200 300 400 500 600 700 800 900 1000 s - parameters (db) frequency (mhz) s11 s22 s12 ? ? ? ? ? ? ? ? ? figure 9. s11, s12 and s22 vs. frequency 110 105 100 95 90 85 80 75 70 65 60 0 50 100 150 200 250 300 350 400 harmonic distortion (dbc) frequency (mhz) hd2 hd3 ? ? ? ? ? ? ? ? ? ? ? figure 10. harmonic distor tion vs. frequency 2vp-p out
preliminary technical data adl5202 rev. pre | page 11 of 13 evaluation board the adl5202 evaluation board is available with software control to program the variable gain control. it is a 4-layer board with split ground plane for analog and digital sections. special care is taken to place the power decoupling capacitors close to the device pins. the board is designed for easy single- ended (through a mini-circuits tc3-1t+ rf transformer) or differential configuration for each channel. evaluation board control software the adl5202 evaluation board is configured with a usb- friendly interface to program the gain of the adl5202. the software gui (see figure 11 ) allows users to select a particular frequency to write to the device and also to read back data from the sdo pin that shows the currently programmed filter setting. the software setup files can be down- loaded from the adl5202 product page at www.analog.com . figure 11. evaluation control software schematics and artwork 50 ohm se 50 ohm se 50 ohm se note: 150 ohm diff pairs made up of 75 ohm se traces. 150 ohm diff pair 150 ohm diff pair 50 ohm se r89 r88 c51 r84 c47 r85 c48 r87 c50 r86 c49 1 3v3 r63 r65 r64 r66 ina+ ina- 28 27 26 25 24 23 22 19 21 20 32 29 31 30 16 15 35 36 13 38 12 39 8 9 17 34 6 pad 4 5 14 37 10 11 33 18 7 40 1 3 2 dut1 1 gnd 1 vpos r34 c31 r38 3 2 1 b3 r42 r44 r48 3 2 1 b4 r33 c30 3 2 1 b0 r37 r41 r32 c29 r31 c28 3 2 1 a3 r36 r40 3 2 1 a0 r46 c33 r50 r52 3 2 1 b1 r43 r47 r45 c32 3 2 1 a4 3 2 1 a1 r35r39 r49r51 r54 c35 r58 r62 3 2 1 b5 r57 r61 3 2 1 b2 r53 c34 r56 r60 3 2 1 a 5 3 2 1 a 2 r55 r59 p2 pwupb 3 2 1 mode1 r14 r19 3 2 1 mode0 r13 r18 3 2 1 pm r12 r17 3 2 1 latchb r11 r16 c22 c23 r28 r22 r29 r25 r23 c19 1 2 3 6 4 t2 inb- r9 inb+ r15 r10 3 2 1 latcha pwupa 3 2 1 p1 r30 c24 c25 c26 c27 r27 c21 c18 r8 r21 r24 r26 r20 c20 1 2 3 6 4 t1 inbp2 0.1uf 0.1uf 0.1uf vouta2p dni dni 0 0.1uf 3v3 0.1uf red 0 0 1k 0.1uf b1 pb4 3v3 b2 dni dni 1k a1 pa2 3v3 a2 dni dni 1k 1k b5 b4 a5 b3 b0 a3 a0 pb2 3v3 pb5 3v3 pa4 3v3 pa1 3v3 dni dni 1k 1k dni dni 1k 1k dni dni dni dni 1k 1k 1k vouta1n b4 b3 b2 b1 b0 a5 a4 a3 1k 1k pb3 dni 1k grn 3v3 vpos pb1 pb0 pa3 dni dni dni dni dni 0.1uf 1k pb6 3v3 1k dni dni dni 3v3 1k 1k 3v3 1k 1k 3v3 1k red 0.1uf 1k 3v3 1k 1k adl5202_prelim_v2 0.1uf a0 a2 a1 b5 pwupb tc3-1t+ 0.1uf 0 vinan vinap vinbn vinbp pm mode0 latcha mode1 latchb 3v3 0.1uf tc3-1t+ pa0 3v3 1k 0 3v3 1k pa7 1k 3v3 1k 1k 3v3 pa6 1k 1k 1k pa5 1k pd6 3v3 pd7 3v3 dni dni dni dni dni dni dni dni dni dni voutb1p 1k a4 vouta1p voutb1n voutb2p 0 voutb2n 0 vouta2n agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd pad fa_a_a2 updn_clk_a_a1 updn_dat_a_a0 latcha vina_neg vina_pos pwupa vouta_pos vouta_neg vouta_neg vouta_pos vpos voutb_pos voutb_neg voutb_neg voutb_pos gnd pwupb vinb_pos vinb_neg latchb updn_dat_b_b0 updn_clk_b_b1 gs0_fa_b_b2 gs1_csb_n_b3 sclk_b4 sdio_b5 pm mode0 mode1 a5 a4 csa_n_a3 agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd 3 2 1 0 ? 0 ? 0 ? 0 ? figure 12. evaluation board schematic
adl5202 preliminary technical data rev. pre | page 12 of 13 150 ohm diff pair 50 ohm se 150 ohm diff pair pos neg 50 ohm se vxa r74 c44 c36 l1 l3 c38 r67 c40 c41 r70 r69 r73 1 2 3 6 4 t3 r77 r79 outb+ outb- r81 outa+ outa- vouta1n vouta1p 0.1uf 1uh tc3-1t+ 1uh 0.1uf vpos v pos 0.1uf 0.1uf dni outa- dni dni 0.1uf dni 0 ? 0 ? 0 ? 0 ? 50 ohm se 50 ohm se 150 ohm diff pair neg 150 ohm diff pair pos vxb c37 l2 c43 r72 l4 r68 c39 c42 r71 r76 c45 1 2 3 6 4 t4 r75 r78 r80 r82 v outb1n vpos 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf tc3-1t+ 1uh vpos 1uh v outb1p dni dni dni dni 0 ? 0 ? 0 ? 0 ? figure 13.rf output detail
preliminary technical data adl5202 rev. pre | page 13 of 13 outline dimensions 40-lea d lea d f r ame c hip scale p ac k a g e [ l f c s p _ w q ] 6 x 6 m m bo d y, ve r y ve r y th i n qu a d (cp-40-10) dimensions shown in millimeters 110708-a 0.50 bsc bot tom vi ew top view pi n 1 indicator exposed pad p i n 1 i n d i c a t o r seati n g plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.23 0.18 6.10 6.00 sq 5.90 0.80 0.75 0.70 0.50 0.40 0.30 0.25 min * 4.45 4.30 sq 4.25 * compliant to jedec standards mo-220-wjjd-6 wit h e x c e p ti o n t o e x p o se d p a d d i m en si o n . 40 1 11 20 21 30 31 10 figure 14. 40-lead lead frame chip scale package [lfcsp_wq] 6 mm 6 mm body, very thin quad (cp-40-10) dimensions shown in millimeters ordering guide model temperature range packag e description package option ADL5202XCPZ-R7 1 ?40c to +85c 40 lead lfcsp_wq, 7 reel cp-40-10 adl5202xcpz-wp 1 ?40c to +85c 40 lead lfcsp_wq, waffle pack cp-40-10 adl5202-evalz 1 ?40c to +85c evaluation board 1 z = rohs compliant part ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr09387-0-3/11(pre)

▲Up To Search▲

Price & Availability of ADL5202XCPZ-R7

	To Download ADL5202XCPZ-R7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .